Another week, another revision of the instruction set.
I’ve been informed that the document that I wrote could use some info about the memory and register layout of the DWMC-16, which I readily accepted. It is a quite useful piece of information to have inside the Instruction Set document.
While I was at it, I decided it would be useful if I combine a few general use registers to use them as 32 bit registers, which are useful for multiplication or division, but also for address modification in combination with the Z Index Register. I had to shuffle the opcodes around however, since I was running out of bits, but oh well…
I also added four new operations into the ALU section, to add some operations that operate over 32 bit data.
Another modification of the opcode is to change the bit testing and bit manipulation operations so that they are using the ALU, rather than specific hardware. It is a bit more work for the Control Logic, but it means I can test and manipulate the bits of ALL registers, not just a specific bit test register.
The final addition to the document is a list of the opcodes in hex format with the mnemonics they are representing.