Categories DWMC-16

DWMC-16: Instruction Set v0.5.1

And again… Here I am, doing another revision of the Instruction set, this time very much centered around the Addressing modes.


RdDestination Register
Rs, Rs2Source Registers
PRProgram Counter
CConstant Number
AddrMemory Address
STStack Pointer
FFlag bit
MSBMost Significant Bit
LSBLeast Significent Bit

Addressing Modes

Since I have eight bits of opcode available, I want to leave six bits for 64 instructions.

Previously, I worried about adding other Addressing modes, compared to the modes in v0.5 with only two bits available, before I realised I can do variable length. I can encode up two addressing modes with two bits, and any more addressing modes with more than two, say four bit. I just have to move the register/flag of Type 2 operations to the lowest four bits of the word.

Adressing ModeExampleBitcodeComment
Registeradd R00, R010b00
Indirect (Register)ld R00, @R010b01
Immediate (Constants)ld R00, 0x0F0F0b1000
Direct Sectorld R00, [0x0F0F]0b1001
Direct Absoluteld R00, [0x0F0F0F]0b1010
Indirect (Z)ld R000b1011
Indexed (Z)ld R00, +0x000F0b1100Adds the second operant to the Z-Index Register
General Adressing Modes

This means that I have seven addressing modes available.

But… Not for all Operations. Going through the list, I did realise that this kind of variable length Addressing mode will not work for four of the branch operations breq/brneq and bgt/bge, as these branch operations need two Registers to compare, which makes it necessary that I put their Addressing modes into its own list…

Adressing ModeExampleBitcode
Direct Sectorbre R00, R01, [0x0F0F]0b00
Direct Absolutebre R00, R01, [0x0F0F0F]0b01
Indirect (Z)bre R00, R010b10
Indexed (Z)bre R00, R01, 0x000F0b11
Addressing Modes for Branch Operations

I certainly dislike having to do it this way, but for the time being, I do not have an idea how to integrate both sides together and keep 6 bits of opcode.

OpCode Encoding

The change of the addressing modes does change the opcode encoding, again, as this time, Type 2 and Type 3 encoded operations are possible with the same operation, depending on the addressing mode. The new Branch Address Modes also make it necessary to add a Type 4 for opcode design.

Type 1: One word, no registers
Word 1Opcode0000000000
Type 2: One Word, one register
Word 1OpcodeAddress Mode00Register/Flag
Type 3: One Word, two registers
Word 1OpcodeAddress ModeSource RegisterDestination Register
Type 4: One Word, one Register, Branch Operation
Word1OpcodeAddress Mode0000Register
Addressing Mode: Direct Local/Constants/Indexed
Word 2Low Address Word (16 bit)/Constants/Indexed
Addressing Mode: Direct (Global)
Word 200000000High Address Word (8 bit)
Word 3Low Address Word (16 bit)

Data Transfer Operations (3 Operations)

CommandMnemonicOperationOpcodeAddress ModesOpTypeAffected Flags
Loadld Rd, Adr/CRd <= Memory[Addr]/C0b000010all Address2None
Storest Rs, Addr16Memory[Addr] <= Rs0b000100all Address2None
Movemv Rd, RsRd <= Rs0b001000N.A.3None

The Load and Store operations certainly allow the use of all Address Modes.

Arythmic Logical Operations (13 Operations)

CommandMnemonicOperationOpcodeAddress ModesOpTypeAffected Flags
Addadd Rd, Rs/CRd <= Rd + Rs/C0b010001all Address3C, QC, HC, TC, Z, N, O
Incrementinc RdRd <= Rd + 10b010010N.A.2C, QC, HC, TC, Z, N, O
Substractsub Rd, Rs/CRd <= Rd – Rs/C0b010011all Address3C, QC, HC, TC, Z, N, O
Decrementdec RdRd <= Rd – 10b010100N.A.2C, QC, HC, TC, Z, N, O
Bitwise ANDand Rd, Rs/CRd <= Rd & Rs/C0b010101all Address3Z
Bitwise ORor Rd, Rs/CRd <= Rd | Rs/C0b010110all Address3Z
Bitwise XORxor Rd, Rs/CRd <= Rd ^ Rs/C0b010111all Address3Z
Bitwise NOTnot RdRd <= ~Rd0b011000N.A.2Z
Logical Shift Leftlsl RdRd <= Rd << 1
LSB <= Carry
Carry <= MSB
0b011001N.A.2C, Z
Logical Shift Rightlsr RdRd <= Rd >> 1
MSB <= Carry
Carry <= LSB
0b011010N.A.2C, Z
Logical Rotate Leftlrl RdRd <= Rd << 1
Logical Rotate Rightlrr RdRd <= Rd >> 1
Logical Switch Bytelsb RdRd[Low] <= Rd[High]
Rd[High] <= Rd[Low]

Here, of course, all operations with two operants allow the use of all conventional addressing modes.

Conditional Branch Instructions (10 Operations)

CommandMnemonicOperationOpcodeAddress ModesOpTypeAffected Flags
Branch local if Flagblf F, Addrif (F == 0): PCL <= Addr/Z0b100000All Branch Address Modes2None
Branch if not Flagbnf F, Addrif (F != 0): PCL <= Addr/Z0b100001All Branch Address Modes2None
Branch if Bitbb B, Addrif (B == 0): PC <= Addr/Z0b100010All Branch Address Modes2None
Branch if not Bitbnb B, Addrif (B !=0): PC <= Addr/Z0b100011All Branch Address Modes2None
Branch if Zero, Decrementbzd Rd, Addrif (Rd == 0): PCL <= Addr/Z
else Rd <= Rd – 1
0b100100All Branch Address Modes2C, Z, N
Branch if not Zero, Decrementbnzd Rd, Addrif (Rd != 0): PCL <= Addr/Z
else Rd <= Rd – 1
0b100101All Branch Address Modes2C, Z, N
Branch if Registers Equalbreq Rs, Rs2, Addrif (Rs == Rs2): PCL <= Addr/Z0b100110All Branch Address Modes4C, Z, N
Branch if Registers not Equalbrne Rs, Rs2, Addrif (Rs != Rs2): PCL <= Addr/Z0b100111All Branch Address Modes4C, Z, N
Branch if greater thenbgt Rs, Rs2, Addrif (Rs > Rs2): PCL <= Addr/Z0b101000All Branch Address Modes4C, Z, N
Branch if greater then or equalbge Rs, Rs2, Addrif (Rs >= Rs2): PCL <= Addr/Z0b101001All Branch Address Modes4C, Z, N

I like to repeat again that I dislike the need to use a separate table for Branch Address Modes, but for the moment it is how it is.

Other Operations ( 11 Operations)

CommandMnemonicOperationOpcodeAddress ModesOpTypeAffected Flags
Jumpjp AddrPCL <= Addr/Z0b1100000b1001, 0b1010, 0b1011, 0x11001None
Jump to Subroutinejls AddrST <= PC + 1;
PCL <= Addr
0b1100010b1001, 0b1010, 0b1011, 0x11001None
ReturnretPC <= ST0b110010N.A.1None
Return from InterruptretiPC <= ST (see post)0b110011N.A.1Any
Push to Stackpush RsST <= Rs0b110100N.A.2None, Any
Pop from Stackpop RdRd <= ST0b110101N.A.2None, Any
Set Flagsf FF <= 10b110101N.A.2Any
Reset Flagrf FF <= 00b110111N.A.2Any
Set Bitsb BR08[B] <= 10b111000N.A.2None
Reset Bitrb BR08[B] <= 00b111001N.A.2None
No operationnopNo operation0xFFN.A.1None

With the two jump operations being the only operations that really need and Address modes, it does not really make any sense to give them all address modes, so I am limiting them to the the two Direct modes, as well as Indirect and Indexed via the Z Index Register.


The number of operations does not change here, but hopefully makes the addressing more powerful.

And I really hope that I find some way to get rid of that damned additional Branch Addressing Mode Table…

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