With my last post being about designing my first Register, and getting a bit deeper into actual hardware, I was missing a few things to go on with my design, namely the Control Signals that I’d need to do work with everything. That meant that, finally, I had to sit down and draw a Block Diagram… It is a relatively simple one that I drew with Draw.io.
A rough count of the control signals I need at least for this version of the Block diagram is about 27.
|AS||ALU Register Select|
|AWE||ALU Write Enable|
|RWE||Register Write Enable|
|RRE||Register Read Enable|
|RS0-RS3||Register Select Lines|
|FS0-FS3||Flag Bit Select Lines|
|FS||Flag Bit Set|
|PCAE||Program Counter Adress Enable|
|SPAE||Stack Pointer Adress Enable|
|ZAE||Z Register Adress Enable|
|IO||IO Select (selects Adress Bus between IO devices and Memory)|
So far, I believe that I have gotten most of the control lines down. Though obviously the block diagram is subject to change in the future, while I continue to work on the project and especially when I throw my self at the control logic.
With another night and back to work, I’ve thought a bit and realized that I can reduce the number of control signals for the Control Logic a little.
The Interrupt Lines are only really needed to access the Interrupt Vectors and internally for the Control Logic can reduce to a single line through an OR Gate.
Similarly, I could combine the Register Select lines and the Flag Bit Select Lines, since they are never needed at the same time and only work in combination with read/write enable lines.
That means that I can reduce the number of signals by ten. And the Clock signal is relatively independent as well.
So internally, the Control Logic would, naively, work with 16 bit of control lines, simplifying things a tiny bit when it comes to the microcode.